InterruptStat Register
| RxFIFOFul | SPDIF Rx FIFO full, can’t be cleared with reg. IntClear. To clear it, read from Rx FIFO. |
| TxEm | SPDIF Tx FIFO empty, can’t be cleared with reg. IntClear. To clear it, write toTx FIFO. |
| LockLoss | SPDIF receiver loss of lock |
| RxFIFOResyn | Rx FIFO resync |
| RxFIFOUnOv | Rx FIFO underrun/overrun |
| UQErr | U/Q Channel framing error |
| UQSync | U/Q Channel sync found |
| QRxOv | Q Channel receive register overrun |
| QRxFul | Q Channel receive register full, can’t be cleared with reg |
| URxOv | U Channel receive register overrun |
| URxFul | U Channel receive register full, can’t be cleared with reg |
| BitErr | SPDIF receiver found parity bit error |
| SymErr | SPDIF receiver found illegal symbol |
| ValNoGood | SPDIF validity flag no good |
| CNew | SPDIF receive change in value of control channel |
| TxResyn | SPDIF Tx FIFO resync |
| TxUnOv | SPDIF Tx FIFO under/overrun |
| Lock | SPDIF receiver’s DPLL is locked |